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| www..com EMBEDDED WRITE-BACK ENHANCED IntelDX4TM PROCESSOR s Up to 100 MHz Operation s Integrated Floating-Point Unit s Speed-Multiplying Technology s 32-Bit RISC Technology Core s 16-Kbyte Write-Back Cache s 3.3 V Core Operation with 5 V Tolerant s SL Technology s Data Bus Parity Generation and Checking s Boundary Scan (JTAG) s 3.3-Volt Processor, 75 MHz, 25 MHz CLK -- 208-Lead Shrink Quad Flat Pack (SQFP) s 3.3-Volt Processor, 100 MHz, 33 MHz CLK I/O Buffers s Burst Bus Cycles s Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices -- 208-Lead Shrink Quad Flat Pack (SQFP) -- 168-Pin Pin Grid Array (PGA) s Binary Compatible with Large Software Base 64-Bit Interunit Transfer Bus 32-Bit Data Bus 32-Bit Data Bus Linear Address CLKMUL Core Clock 32 Clock Multiplier CLK DataShee .com PCD PWT 2 Barrel Shifter Base/ Index Bus 32 Segmentation Unit Bus Interface Cache Unit 32 A31-A2 BE3#- BE0# Paging Unit 20 Register File Descriptor Registers Address Drivers Write Buffers 4 x 32 D31-D0 Physical Address ALU Limit and Attribute PLA Translation Lookaside Buffer 16 Kbyte Cache 32 32 Data Bus Transceivers Bus Control ADS# W/R# D/C# M/IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# FERR# IGNNE# STPCLK# Displacement Bus 32 128 Request Sequencer Prefetcher MicroInstruction 32-Byte Code Queue 2 x 16 Bytes Burst Bus Control BRDY# BLAST# Floating Point Unit Control & Protection Test Unit Code Stream Bus Size Control BS16# BS8# Instruction Decode 24 Cache Control KEN# FLUSH# AHOLD EADS# CACHE# HITM# INV WB/WT# Floating Point Register File Control ROM Decoded Instruction Path Parity Generation and Control Boundary Scan Control PCHK# DP3-DP0 TCK TMS TDI TDO .com Figure 1. Embedded Write-Back Enhanced IntelDX4TM Processor Block Diagram (c) INTEL CORPORATION, 2004 August 2004 A3232-01 .com Order Number: 272771-003 DataSheet 4 U .com www..com Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in t4U.com Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright .com or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Embedded Write-Back Enhanced IntelDX4TM processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1997, 2004 *Third-party brands and names are the property of their respective owners. DataShee .com .com DataSheet 4 U .com www..com Contents EMBEDDED WRITE-BACK ENHANCED IntelDX4TM PROCESSOR 1.0 INTRODUCTION ........................................................................................................................................ 1 1.1 Features ............................................................................................................................................. 1 1.2 Family Members ........................................................................................................... ...................... 2 2.0 HOW TO USE THIS DOCUMENT ................................................................................................. ............ 3 3.0 PIN DESCRIPTIONS ......................................................................................................... ........................ 3 3.1 Pin Assignments ................................................................................................................................. 3 3.2 Pin Quick Reference ......................................................................................................................... 16 4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 26 4.1 CPUID Instruction ............................................................................................................................. 26 4.1.1 Operation of the CPUID Instruction ....................................................................................... 26 4.2 Identification After Reset .................................................................................................................. 28 4.3 Boundary Scan (JTAG) .................................................................................................................... 28 4.3.1 Device Identification ............................................................................................................... 28 4.3.2 Boundary Scan Register Bits and Bit Order ........................................................................... 29 t4U.com 5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 30 5.1 Maximum Ratings ............................................................................................................................. 30 DataShee 5.2 DC Specifications ............................................................................................................................. 30 .com 5.3 AC Specifications ............................................................................................................................. 33 5.4 Capacitive Derating Curves .............................................................................................................. 40 6.0 MECHANICAL DATA .............................................................................................................................. 42 6.1 Package Dimensions ........................................................................................................................ 42 6.2 Package Thermal Specifications ...................................................................................................... 44 FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Embedded Write-Back Enhanced IntelDX4TM Processor Block Diagram ................................... i Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4TM Processor ................................................................................................................ 4 Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced IntelDX4TM Processor .............................................................................................................. 10 CLK Waveform ........................................................................................................................ 36 Input Setup and Hold Timing ................................................................................................... 36 Input Setup and Hold Timing ................................................................................................... 37 PCHK# Valid Delay Timing ...................................................................................................... 37 Output Valid Delay Timing ....................................................................................................... 38 Maximum Float Delay Timing .................................................................................................. 38 TCK Waveform ........................................................................................................................ 39 Test Signal Timing Diagram .................................................................................................... 39 .com .com DataSheet 4 U .com iii www..com Contents Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition ..................................................................................................... 40 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition ..................................................................................................... 40 Typical Loading Delay versus Load Capacitance in Mixed Voltage System ........................... 41 208-Lead SQFP Package Dimensions .................................................................................... 42 Principal Dimensions and Data for 168-Pin Grid Array Package ............................................. 43 The Embedded Write-Back Enhanced IntelDX4TM Processor Family ....................................... 2 Pinout Differences for 208-Lead SQFP Package ...................................................................... 5 Pin Assignment for 208-Lead SQFP Package ........................................................................... 6 Pin Cross Reference for 208-Lead SQFP Package ................................................................... 8 Pinout Differences for 168-Pin PGA Package ......................................................................... 11 Pin Assignment for 168-Pin PGA Package .............................................................................. 12 Pin Cross Reference for 168-Pin PGA Package ...................................................................... 14 Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions ............................. 16 Output Pins .............................................................................................................................. 24 Input/Output Pins ..................................................................................................................... 24 Test Pins .................................................................................................................................. 25 Input Pins ................................................................................................................................. 25 CPUID Instruction Description ................................................................................................. 26 Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode) ........... 28 Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode) ............... 29 Absolute Maximum Ratings ..................................................................................................... 30 Operating Supply Voltages ...................................................................................................... 30 DC Specifications ..................................................................................................................... 31 ICC Values ................................................................................................................................ 32 AC Characteristics ................................................................................................................... 33 AC Specifications for the Test Access Port ............................................................................. 35 168-Pin Ceramic PGA Package Dimensions ........................................................................... 43 Ceramic PGA Package Dimension Symbols ........................................................................... 44 Thermal Resistance, JA (C/W) ............................................................................................. 45 Thermal Resistance, JC (C/W) ............................................................................................. 45 Maximum Tambient, TA max (C) ............................................................................................... 45 t4U.com Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. DataShee .com Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. .com iv .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor 1.0 INTRODUCTION 1.1 Features The embedded Write-Back Enhanced IntelDX4TM processor provides high performance to 32-bit, embedded applications. Designed for applications that need a floating-point unit, the processor is ideal for embedded designs running DOS*, Microsoft Windows*, OS/2*, or UNIX* applications written for the Intel architecture. Projects can be completed quickly using the wide range of software tools, utilities, assemblers and compilers that are available for desktop computer systems. Also, developers can find advantages in using existing chipsets and peripheral components in their embedded designs. The Embedded Write-Back Enhanced IntelDX4 processor is binary compatible with the Intel386TM and earlier Intel processors. Compared with the Intel386 processor, it provides faster execution of many commonly-used instructions. It also provides the benefits of an integrated, 16-Kbyte, write-back cache for code and data. Its data bus can operate in burst mode which provides up to 106-Mbyte-persecond transfers for cache-line fills and instruction prefetches. The Embedded Write-Back Enhanced IntelDX4 processor offers these features: * 32-bit RISC-Technology Core -- The Embedded Write-Back Enhanced IntelDX4 processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. * Single Cycle Execution -- Many instructions execute in a single clock cycle. * Instruction Pipelining -- Overlapped instruction fetching, decoding, address translation and execution. * On-Chip Floating-Point Unit -- Intel486TM processors support the 32-, 64-, and 80-bit formats specified in IEEE standard 754. The unit is binary compatible with the 8087, Intel287TM, Intel387TM coprocessors, and Intel OverDrive(R) processor. t4U.com * On-Chip Cache with Cache Consistency Support -- A 16-Kbyte internal cache is used for both data and instructions. It is configurable to be ataShee D write-back or write-through on a line-by-line basis. The internal cache implements a modified MESI Intel's SL technology is incorporated in the .com protocol, which is applicable to uniprocessor Embedded Write-Back Enhanced IntelDX4 systems. Cache hits provide zero wait-state processor. Utilizing Intel's System Management access times for data within the cache. Bus activity Mode (SMM) enables designers to develop energyis tracked to detect alterations in the memory efficient systems. represented by the internal cache. The internal cache can be invalidated or flushed so that an Two component packages are available: external cache controller can maintain cache * 168-pin Pin Grid Array (PGA) consistency. * 208-lead Shrink Quad Flat Pack (SQFP) * External Cache Control -- Write-back and flush The processor operates at either two or three times the external bus frequency. At two times the external bus frequency the processor operates up to 66 MHz, (33-MHz CLK). At three times the external bus frequency the processor operates up to 100 MHz (33-MHz CLK). controls for an external cache are provided so the processor can maintain cache consistency. * On-Chip Memory Management Unit -- Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both memory segmentation and paging are supported. * Burst Cycles -- Burst transfers allow a new double-word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. Data written from the processor to memory can also be burst transfers. * Write Buffers -- The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. 1 .com .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor * Bus Backoff -- When another bus master needs control of the bus during a processor initiated bus cycle, the Embedded Write-Back Enhanced IntelDX4 processor floats its bus signals, then restarts the cycle when the bus becomes available again. * Instruction Restart -- Programs can continue execution following an exception generated by an unsuccessful attempt to access memory. This feature is important for supporting demand-paged virtual memory applications. * Dynamic Bus Sizing -- External controllers can dynamically alter the effective width of the data bus. Bus widths of 8, 16, or 32 bits can be used. * Boundary Scan (JTAG) -- Boundary Scan provides in-circuit testing of components on printed circuit boards. The Intel Boundary Scan implementation conforms with the IEEE Standard Test Access Port and Boundary Scan Architecture. * Enhanced Bus Mode -- The definitions of some signals have been changed to support write-back cache mode. * Stop Clock -- The Embedded Write-Back Enhanced IntelDX4 processor has a stop clock control mechanism that provides two low-power states: a Stop Grant state (20-50 mA typical, depending on input clock frequency) and a Stop Clock state (~600 A typical, with input clock frequency of 0 MHz). * Auto HALT Power Down -- After the execution of a HALT instruction, the Embedded Write-Back Enhanced IntelDX4 processor issues a normal Halt bus cycle and the clock input to the processor core is automatically stopped, causing the processor to enter the Auto HALT Power Down state (20-50 mA typical, depending on input clock frequency). * Auto Idle Power Down -- This function allows the processor to reduce the core frequency to the bus frequency when both the core and bus are idle. Auto Idle Power Down is software transparent and does not affect processor performance. Auto Idle Power Down provides an average power savings of 10% and is only applicable to clock multiplied processors. t4U.com SL technology provides these features: Intel's * Intel System Management Mode (SMM) -- A 1.2 Family Members unique Intel architecture operating mode provides .com a dedicated special purpose interrupt and address Table 1 shows the Embedded Write-Back Enhanced space that can be used to implement intelligent IntelDX4 processors and briefly describes their power management and other enhanced functions characteristics. in a manner that is completely transparent to the operating system and applications software. * I/O Restart -- An I/O instruction interrupted by a System Management Interrupt (SMI#) can automatically be restarted following the execution of the RSM instruction. DataShee Table 1. The Embedded Write-Back Enhanced IntelDX4TM Processor Family Product x80486DX4WB75 x80486DX4WB100 x80486DX4WB100 Supply Voltage VCC Maximum Processor Frequency 75 MHz 100 MHz 100 MHz Maximum External Bus Frequency 25 MHz 33 MHz 33 MHz Package 208-Lead SQFP 208-Lead SQFP 168-Pin PGA 3.3 V 3.3 V 3.3 V NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". .com 2 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor 2.0 HOW TO USE THIS DOCUMENT 3.0 3.1 PIN DESCRIPTIONS Pin Assignments For a complete set of documentation related to the Embedded Write-Back Enhanced IntelDX4 processor, use this document in conjunction with the following reference documents: * Embedded Intel486TM Processor Family Developer's Manual -- Order No. 273021 * Embedded Intel486TM Processor Hardware Reference Manual -- Order No. 273025 * Intel486 Microprocessor Family Programmer's Reference Manual -- Order No. 240486 * Intel Application Note AP-485 -- Intel Processor Identification with the CPUID Instruction -- Order No. 241618 The information in the reference documents for the IntelDX4 processor applies to the Embedded WriteBack Enhanced IntelDX4 processor. Some of the IntelDX4 processor information is duplicated in this document to minimize the dependence on the reference documents. The following figures and tables show the pin assignments of each package type for the Embedded Write-Back Enhanced IntelDX4 processor. Tables are provided showing the pin differences between the Embedded Write-Back Enhanced IntelDX4 processor and other embedded Intel486 processor products. 208-Lead SQFP - Quad Flat Pack * Figure 2, Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4TM Processor (pg. 4) * Table 2, Pinout Differences for 208-Lead SQFP Package (pg. 5) * Table 3, Pin Assignment for 208-Lead SQFP Package (pg. 6) * Table 4, Pin Cross Reference for 208-Lead SQFP Package (pg. 8) 168-Pin PGA - Pin Grid Array t4U.com DataShee .com 3, Package Diagram for 168-Pin PGA * Figure Embedded Write-Back Enhanced IntelDX4TM Processor (pg. 10) * Table 5, Pinout Differences for 168-Pin PGA Package (pg. 11) * Table 6, Pin Assignment for 168-Pin PGA Package (pg. 12) * Table 7, Pin Cross Reference for 168-Pin PGA Package (pg. 14) .com .com DataSheet 4 U .com 3 www..com Embedded Write-Back Enhanced IntelDX4TM Processor t4U.com VSS VCC VCC5 PCHK# BRDY# BOFF# BS16# BS8# VCC VSS CLKMUL RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK VCC HLDA W/R# VSS VCC BREQ BE0# BE1# BE2# BE3# VCC VSS M/IO# VCC D/C# PWT PCD VCC VSS VCC VCC EADS# A20M# RESET FLUSH# INTR NMI VSS 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VSS LOCK# PLOCK# VCC BLAST# ADS# A2 VSS VCC VSS VCC A3 A4 A5 RESERVED# A6 A7 VCC A8 VSS VCC A9 A10 VCC VSS VCC A11 VSS A12 VCC A13 A14 VCC VSS A15 A16 VCC A17 VSS VCC TDI TMS A18 A19 A20 VCC VCC A21 A22 A23 A24 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4TM Processor Top View .com 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSS VCC A25 A26 A27 A28 VCC A29 A30 A31 VSS DP0 D0 D1 D2 D3 D4 VCC VSS VCC VCC VSS VCC VCC VSS VCC D5 D6 VCC NC D7 DP1 D8 D9 VSS VCC VSS D10 D11 D12 D13 VSS VCC D14 D15 VCC VSS DP2 D16 VSS VCC VSS DataShee VSS VCC VSS VCC VSS SRESET SMIACT# VCC VSS VCC HITM# WB/WT# SMI# FERR# NC TDO VCC CACHE# INV IGNNE# STPCLK# D31 D30 VSS VCC D29 D28 VCC VSS VCC D27 D26 D25 VCC D24 VSS VCC DP3 D23 D22 D21 VSS VCC NC VSS VCC D20 D19 D18 VCC D17 VSS 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 A3230-01 Figure 2. Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4TM Processor .com 4 DataSheet 4 U .com .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 2. Pinout Differences for 208-Lead SQFP Package Pin # 3 11 63 64 66 70 71 72 Embedded Intel486TM SX Processor VCC1 INC2 INC INC INC INC INC INC Embedded IntelDX2TM Processor VCC INC INC INC FERR# INC INC IGNNE# Embedded Write-Back Enhanced IntelDX4TM Processor VCC5 CLKMUL HITM# WB/WT# FERR# CACHE# INV IGNNE# t4U.com NOTES: 1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to the VCC plane. 2. INC. Internal No Connect. These pins are not connected to any internal pad. However, signals are defined for the location of the INC pins in the embedded IntelDX4 processor. One system design can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used. DataShee .com .com .com DataSheet 4 U .com 5 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 1 of 2) Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 Description VSS VCC VCC5 PCHK# BRDY# BOFF# BS16# BS8# VCC VSS CLKMUL RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK VCC HLDA W/R# VSS VCC BREQ BE0# BE1# BE2# BE3# VCC Pin# 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Description VSS VCC VSS VCC VSS SRESET SMIACT# VCC VSS VCC HITM# WB/WT# SMI# FERR# NC1 TDO VCC CACHE# INV IGNNE# STPCLK# D31 D30 VSS VCC D29 D28 VCC VSS VCC D27 D26 D25 VCC D24 Pin# 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Description VSS VCC VSS D16 DP2 VSS VCC D15 D14 VCC VSS D13 D12 D11 D10 VSS VCC VSS D9 D8 DP1 D7 NC1 VCC D6 D5 VCC VSS VCC VCC VSS VCC VCC VSS VCC Pin# 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 Description VSS A24 A23 A22 A21 VCC VCC A20 A19 A18 TMS TDI VCC VSS A17 VCC A16 A15 VSS VCC A14 A13 VCC A12 VSS A11 VCC VSS VCC A10 A9 VCC VSS A8 VCC t4U.com 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DataShee 120 .com 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 .com 35 6 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2) Pin# 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Description VSS M/IO# VCC D/C# PWT PCD VCC VSS VCC VCC EADS# A20M# RESET FLUSH# INTR NMI VSS Pin# 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Description VSS VCC DP3 D23 D22 D21 VSS VCC Pin# 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Description D4 D3 D2 D1 D0 DP0 VSS A31 A30 A29 VCC A28 A27 A26 A25 VCC VSS Pin# 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Description A7 A6 RESERVED# A5 A4 A3 VCC VSS VCC VSS A2 ADS# BLAST# VCC PLOCK# LOCK# VSS NC1 VSS VCC D20 D19 D18 VCC D17 t4U.com 50 51 52 DataShee .com VSS 156 NOTE: 1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors. .com .com DataSheet 4 U .com 7 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2) Address A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Pin # 202 197 196 195 193 192 190 187 186 182 180 178 177 174 173 171 166 165 164 161 160 159 158 154 153 152 151 149 148 147 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 Pin # 144 143 142 141 140 130 129 126 124 123 119 118 117 116 113 112 108 103 101 100 99 93 92 91 87 85 84 83 79 78 75 74 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CACHE# Pin # 47 203 17 31 32 33 34 204 6 5 30 7 8 70 NC 67 96 127 VCC5 3 VCC 2 9 14 19 20 22 23 25 29 35 38 42 44 45 54 56 60 62 69 77 80 82 86 89 95 98 102 106 111 114 121 128 131 VSS 1 10 15 21 28 36 43 52 53 55 57 61 76 81 88 94 97 104 105 107 110 115 120 122 132 135 138 146 156 157 170 175 181 t4U.com A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 DataShee CLK 24 .com CLKMUL D/C# DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR INV KEN# LOCK# M/IO# 11 39 145 125 109 90 46 66 49 63 26 16 72 50 71 13 207 37 .com D31 8 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 2 of 2) Address Pin # Data Pin # Control NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# TCK Pin # 51 41 4 206 40 12 194 48 65 59 58 73 18 168 68 NC V CC5 VCC 133 134 136 137 139 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 V SS 184 189 199 201 208 t4U.com TDI TDO DataShee .com TMS 167 WB/WT# W/R# 64 27 .com .com DataSheet 4 U .com 9 www..com Embedded Write-Back Enhanced IntelDX4TM Processor A D20 B D19 C D11 D D9 E VSS F DP1 G VSS H VSS J VCC5 K VSS L VSS M VSS N P Q R A28 S A27 1 D2 D0 A31 1 2 D22 D21 D18 D13 VCC D8 VCC D3 D5 VCC D6 VCC D1 A29 VSS A25 A26 2 3 TCK VSS CLK D17 D10 D15 D12 DP2 D16 D14 D7 D4 DP0 A30 A17 VCC A23 3 4 D23 VSS VCC A19 VSS VOLDET 4 5 DP3 VSS VCC A21 A18 A14 5 6 D24 D25 D27 A24 VCC VSS 6 7 VSS VCC D26 A22 A15 A12 8 D29 D31 D28 168-Pin PGA Embedded Write-Back Enhanced IntelDX4TM Processor 7 A20 VCC VSS 8 9 VSS INV VCC SMI# D30 A16 VCC VSS 9 t4U.com 10 11 SRESET A13 VCC VSS Pin Side View VSS VCC RESERVED# 10 DataShee .com A9 VCC VSS 11 12 HITM# CACHE# SMIACT# A5 A11 VSS 12 13 INC WB/WT# NC A7 A8 A10 13 14 TDI TMS FERR# A2 VCC A3 VSS A6 14 15 IGNNE# NMI FLUSH# A20M# HOLD KEN# STPCLK# BRDY# BE2# BE0# PWT D/C# LOCK# HLDA BREQ 15 16 INTR TDO RESET BS8# VCC RDY# VCC VCC BE1# VCC VCC VCC M/IO# VCC PLOCK# BLAST# A4 16 17 AHOLD EADS# BS16# BOFF# VSS BE3# VSS VSS PCD VSS VSS VSS W/R# VSS PCHK# CLKMUL ADS# 17 A B C D E F G H J K L M N P Q R S A3231-01 Figure 3. Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced IntelDX4TM Processor .com 10 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 5. Pinout Differences for 168-Pin PGA Package Pin # A10 A12 B12 B13 J1 R17 S4 Embedded IntelDX2TM Processor INC INC INC INC V CC INC NC Embedded Write-Back Enhanced IntelDX4TM Processor INV HITM# CACHE# WB/WT# V CC5 CLKMUL VOLDET t4U.com DataShee .com .com .com DataSheet 4 U .com 11 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2) Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Description D20 D22 TCK D23 DP3 D24 VSS Pin # D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G15 G17 H1 H2 H3 H15 H16 H17 J1 J2 J3 J15 J16 J17 K1 K2 K3 K15 K16 K17 L1 L2 Description BOFF# VSS VCC Pin # P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 Description A29 A30 HLDA VCC VSS D10 HOLD VCC VSS A31 VSS D29 VSS DP1 D8 D15 KEN# RDY# BE3# VSS VCC A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7 A2 BREQ PLOCK# PCHK# A28 A25 VCC VSS INV VSS HITM# INC TDI IGNNE# INTR AHOLD D19 D21 VSS VSS VSS t4U.com A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 D12 STPCLK# VSS VSS DataShee G16 VCC .com D3 DP2 BRDY# VCC VSS VCC5 D25 VCC D31 VCC SMI# VCC D5 D16 BE2# BE1# PCD VSS VCC A18 VCC CACHE# WB/WT# TMS NMI TDO EADS# D11 D18 CLK VCC VCC A15 VCC VCC VCC VCC D14 BE0# VCC VSS VSS A11 A8 VCC A3 BLAST# CLKMUL .com D6 12 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2) Pin # C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 Description D27 D26 D28 D30 SRESET RESERVED# SMIACT# NC FERR# FLUSH# RESET BS16# D9 D13 D17 A20M# BS8# Pin # L3 L15 L16 L17 M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1 Description D7 PWT VCC VSS VSS VCC Pin # S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Description A27 A26 A23 VOLDET A14 VSS D4 D/C# VCC VSS A12 VSS VSS VSS VSS VSS D2 D1 DP0 LOCK# M/IO# W/R# D0 A10 VSS A6 A4 ADS# t4U.com DataShee .com .com .com DataSheet 4 U .com 13 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2) Addres s A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 Pin # Q14 R15 S16 Q12 S15 Q13 R13 Q11 S13 R12 S7 Q10 S5 R7 Q9 Q3 R5 Q4 Q8 Q5 Q7 S3 Q6 R2 S2 S1 R1 P2 P3 Q1 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 Pin # P1 N2 N1 H2 M3 J2 L2 L3 F2 D1 E3 C1 G3 D2 K3 F3 J3 D3 C2 B1 A1 B2 A2 A4 A6 B6 C7 C6 C8 A8 C9 B8 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK CLKMUL Pin # D15 S17 A17 K15 J16 J15 F17 R16 D17 H15 Q15 C17 D16 C3 NC C13 INC A13 Vcc5 J1 Vcc B7 B9 B11 C4 C5 E2 E16 G2 G16 H16 K2 K16 L16 M2 M16 P16 R3 R6 R8 R9 R10 R11 R14 Vss A7 A9 A11 B3 B4 B5 E1 E17 G1 G17 H1 H17 K1 K17 L1 L17 M1 M17 P17 Q2 R4 S6 S8 S9 S10 S11 S12 S14 t4U.com A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 DataShee .com R17 B12 M15 N3 F1 H3 A5 B17 C14 C15 A12 P15 E15 A15 A16 A10 F15 N15 N16 CACHE# D/C# DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR INV KEN# LOCK# M/IO# .com D31 14 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 2 of 2) Addres s Pin # Data Pin # Control NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# Pin # B15 J17 Q17 Q16 L15 F16 C11 C16 B10 C12 C10 G15 A3 A14 NC INC Vcc5 Vcc Vss t4U.com TCK TDI DataShee TDO B16 .com TMS VOLDET WB/WT# W/R# B14 S4 B13 N17 .com .com DataSheet 4 U .com 15 www..com Embedded Write-Back Enhanced IntelDX4TM Processor 3.2 Pin Quick Reference The following is a brief pin description. For detailed signal descriptions refer to Appendix A, "Signal Descriptions," in the Embedded Intel486TM Processor Family Developer's Manual, order No. 273021. Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 1 of 8) Symbol CLK Type I Name and Function Clock provides the fundamental timing and internal operating frequency for the Embedded Write-Back Enhanced IntelDX4 processor. All external timing parameters are specified with respect to the rising edge of CLK. Address Lines A31-A2, together with the byte enable signals, BE3#-BE0#, define the physical area of memory or input/output space accessed. Address lines A31-A4 are used to drive addresses into the Embedded Write-Back Enhanced IntelDX4 processor to perform cache line invalidation. Input signals must meet setup and hold times t22 and t23. A31-A2 are not driven during bus or address hold. Byte Enable signals indicate active bytes during read and write cycles. During the first cycle of a cache fill, the external system should assume that all byte enables are active. BE3#-BE0# are active LOW and are not driven during bus hold. BE3# applies to D31-D24 BE2# applies to D23-D16 BE1# applies to D15-D8 .com BE0# applies to D7-D0 DATA BUS D31-D0 I/O Data Lines. D7-D0 define the least significant byte of the data bus; D31-D24 define the most significant byte of the data bus. These signals must meet setup and hold times t22 and t23 for proper operation on reads. These pins are driven during the second and subsequent clocks of write cycles. There is one Data Parity pin for each byte of the data bus. Data parity is generated on all write data cycles with the same timing as the data driven by the Embedded Write-Back Enhanced IntelDX4 processor. Even parity information must be driven back into the processor on the data parity pins with the same timing as read information to ensure that the correct parity check status is indicated by the Embedded Write-Back Enhanced IntelDX4 processor. The signals read on these pins do not affect program execution. Input signals must meet setup and hold times t22 and t23. DP3-DP0 must be connected to VCC through a pull-up resistor in systems that do not use parity. DP3-DP0 are active HIGH and are driven during the second and subsequent clocks of write cycles. PCHK# O Parity Status is driven on the PCHK# pin the clock after ready for read operations. The parity status is for data sampled at the end of the previous clock. A parity error is indicated by PCHK# being LOW. Parity status is only checked for enabled bytes as indicated by the byte enable and bus size signals. PCHK# is valid only in the clock immediately after read data is returned to the processor. At all other times PCHK# is inactive (HIGH). PCHK# is never floated. ADDRESS BUS A31-A4 A3-A2 I/O O BE3# BE2# BE1# BE0# O O O O t4U.com DataShee DATA PARITY DP3-DP0 I/O .com 16 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 2 of 8) Symbol M/IO# D/C# W/R# Type O O O Name and Function Memory/Input-Output, Data/Control and Write/Read lines are the primary bus definition signals. These signals are driven valid as the ADS# signal is asserted. M/IO# 0 0 0 0 1 1 1 1 D/C# 0 0 1 1 0 0 1 1 Cycle Name Shutdown W/R# 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge HALT/Special Cycle (see details below) I/O Read I/O Write Code Read Reserved Memory Read Memory Write HALT/Special Cycle BE3# - BE0# 1110 1011 1011 A4-A2 000 000 100 BUS CYCLE DEFINITION t4U.com LOCK# O HALT Stop Grant bus cycle DataShee Bus Lock indicates that the current bus cycle is locked. The Embedded Write.com Back Enhanced IntelDX4 processor does not allow a bus hold when LOCK# is asserted (address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW and not driven during bus hold. Locked read cycles are not transformed into cache fill cycles when KEN# is returned active. Pseudo-Lock indicates that the current bus transaction requires more than one bus cycle to complete. For the Embedded Write-Back Enhanced IntelDX4 processor, examples of such operations are segment table descriptor reads (64 bits) and cache line fills (128 bits). For Intel486 processors with on-chip FloatingPoint Unit, floating-point long reads and writes (64 bits) also require more than one bus cycle to complete. The Embedded Write-Back Enhanced IntelDX4 processor drives PLOCK# active until the addresses for the last bus cycle of the transaction are driven, regardless of whether RDY# or BRDY# have been returned. Normally PLOCK# and BLAST# are inverse of each other. However, during the first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip Floating-Point Unit) both PLOCK# and BLAST# are asserted. PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK# is active LOW and is not driven during bus hold. PLOCK# O BUS CONTROL ADS# O Address Status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are driven. ADS# is active LOW and not driven during bus hold. .com .com DataSheet 4 U .com 17 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 3 of 8) Symbol RDY# Type I Name and Function Non-burst Ready input indicates that the current bus cycle is complete. RDY# indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted data from the Embedded Write-Back Enhanced IntelDX4 processor in response to a write. RDY# is ignored when the bus is idle and at the end of the first clock of the bus cycle. RDY# is active during address hold. Data can be returned to the Embedded WriteBack Enhanced IntelDX4 processor while AHOLD is active. RDY# is active LOW and is not provided with an internal pull-up resistor. RDY# must satisfy setup and hold times t16 and t17 for proper chip operation. BURST CONTROL BRDY# I Burst Ready input performs the same function during a burst cycle that RDY# performs during a non-burst cycle. BRDY# indicates that the external system has presented valid data in response to a read or that the external system has accepted data in response to a write. BRDY# is ignored when the bus is idle and at the end of the first clock in a bus cycle. BRDY# is sampled in the second and subsequent clocks of a burst cycle. Data presented on the data bus is strobed into the Embedded Write-Back Enhanced IntelDX4 processor when BRDY# is sampled active. If RDY# is returned simultaneously with BRDY#, BRDY# is ignored and the burst cycle is prematurely aborted. BRDY# is active LOW and is provided with a small pull-up resistor. BRDY# must satisfy the setup and hold times t16 and t17. .com BLAST# O Burst Last signal indicates that the next time BRDY# is returned, the burst bus cycle is complete. BLAST# is active for both burst and non-burst bus cycles. BLAST# is active LOW and is not driven during bus hold. Reset input forces the Embedded Write-Back Enhanced IntelDX4 processorto begin execution at a known state. The processor cannot begin executing instructions until at least 1 ms after VCC, and CLK have reached their proper DC and AC specifications. The RESET pin must remain active during this time to ensure proper processor operation. However, for warm resets, RESET should remain active for at least 15 CLK periods. RESET is active HIGH. RESET is asynchronous but must meet setup and hold times t20 and t21 for recognition in any specific clock. Maskable Interrupt indicates that an external interrupt has been generated. When the internal interrupt flag is set in EFLAGS, active interrupt processing is initiated. The Embedded Write-Back Enhanced IntelDX4 processorgenerates two locked interrupt acknowledge bus cycles in response to the INTR pin going active. INTR must remain active until the interrupt acknowledges have been performed to ensure processor recognition of the interrupt. INTR is active HIGH and is not provided with an internal pull-down resistor. INTR is asynchronous, but must meet setup and hold times t20 and t21 for recognition in any specific clock. NMI I Non-Maskable Interrupt request signal indicates that an external non-maskable interrupt has been generated. NMI is rising-edge sensitive and must be held LOW for at least four CLK periods before this rising edge. NMI is not provided with an internal pull-down resistor. NMI is asynchronous, but must meet setup and hold times t20 and t21 for recognition in any specific clock. t4U.com DataShee INTERRUPTS RESET I INTR I .com 18 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 4 of 8) Symbol SRESET Type I Name and Function Soft Reset pin duplicates all functionality of the RESET pin except that the SMBASE register retains its previous value. For soft resets, SRESET must remain active for at least 15 CLK periods. SRESET is active HIGH. SRESET is asynchronous but must meet setup and hold times t20 and t21 for recognition in any specific clock. System Management Interrupt input invokes System Management Mode (SMM). SMI# is a falling-edge triggered signal which forces the Embedded Write-Back Enhanced IntelDX4 processorinto SMM at the completion of the current instruction. SMI# is recognized on an instruction boundary and at each iteration for repeat string instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a currently executing SMM. The Embedded Write-Back Enhanced IntelDX4 processorlatches the falling edge of one pending SMI# signal while it is executing an existing SMI#. The nested SMI# is not recognized until after the execution of a Resume (RSM) instruction. System Management Interrupt Active, an active LOW output, indicates that the Embedded Write-Back Enhanced IntelDX4 processoris operating in SMM. It is asserted when the processor begins to execute the SMI# state save sequence and remains active LOW until the processor executes the last state restore cycle out of SMRAM. SMI# I SMIACT# O t4U.com STPCLK# I Stop Clock Request input signal indicates a request was made to turn off or DataShee change the CLK input frequency. When the Embedded Write-Back Enhanced IntelDX4 processorrecognizes a STPCLK#, it stops execution on the next .com instruction boundary (unless superseded by a higher priority interrupt), empties all internal pipelines and write buffers, and generates a Stop Grant bus cycle. STPCLK# is active LOW. STPCLK# must be pulled high via a 10-KW pullup resistor. STPCLK# is an asynchronous signal, but must remain active until the Embedded Write-Back Enhanced IntelDX4 processor issues the Stop Grant bus cycle. STPCLK# may be de-asserted at any time after the processor has issued the Stop Grant bus cycle. Bus Request signal indicates that the Embedded Write-Back Enhanced IntelDX4 processorhas internally generated a bus request. BREQ is generated whether or not the processor is driving the bus. BREQ is active HIGH and is never floated. Bus Hold Request allows another bus master complete control of the Embedded Write-Back Enhanced IntelDX4 processorbus. In response to HOLD going active, the processor floats most of its output and input/output pins. HLDA is asserted after completing the current bus cycle, burst cycle or sequence of locked cycles. The Embedded Write-Back Enhanced IntelDX4 processorremains in this state until HOLD is de-asserted. HOLD is active HIGH and is not provided with an internal pull-down resistor. HOLD must satisfy setup and hold times t18 and t19 for proper operation. Hold Acknowledge goes active in response to a hold request presented on the HOLD pin. HLDA indicates that the Embedded Write-Back Enhanced IntelDX4 processor has given the bus to another local bus master. HLDA is driven active in the same clock that the processor floats its bus. HLDA is driven inactive when leaving bus hold. HLDA is active HIGH and remains driven during bus hold. BUS ARBITRATION BREQ O HOLD I HLDA O .com .com DataSheet 4 U .com 19 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 5 of 8) Symbol BOFF# Type I Name and Function Backoff input forces the Embedded Write-Back Enhanced IntelDX4 processor to float its bus in the next clock. The processor floats all pins normally floated during bus hold but HLDA is not asserted in response to BOFF#. BOFF# has higher priority than RDY# or BRDY#; if both are returned in the same clock, BOFF# takes effect. The Embedded Write-Back Enhanced IntelDX4 processor remains in bus hold until BOFF# is negated. If a bus cycle is in progress when BOFF# is asserted the cycle is restarted. BOFF# is active LOW and must meet setup and hold times t18 and t19 for proper operation. Address Hold request allows another bus master access to the Embedded WriteBack Enhanced IntelDX4 processor's address bus for a cache invalidation cycle. The processor stops driving its address bus in the clock following AHOLD going active. Only the address bus is floated during address hold, the remainder of the bus remains active. AHOLD is active HIGH and is provided with a small internal pull-down resistor. For proper operation, AHOLD must meet setup and hold times t18 and t19. External Address - This signal indicates that a valid external address has been driven onto the Embedded Write-Back Enhanced IntelDX4 processor address pins. This address is used to perform an internal cache invalidation cycle. EADS# is active LOW and is provided with an internal pull-up resistor. EADS# must satisfy setup and hold times t12 and t13 for proper operation. CACHE INVALIDATION AHOLD I EADS# I t4U.com CACHE CONTROL KEN# I DataShee .com Cache Enable pin is used to determine whether the current cycle is cacheable. When the Embedded Write-Back Enhanced IntelDX4 processorgenerates a cycle that can be cached and KEN# is active one clock before RDY# or BRDY# during the first transfer of the cycle, the cycle becomes a cache line fill cycle. Returning KEN# active one clock before RDY# during the last read in the cache line fill causes the line to be placed in the on-chip cache. KEN# is active LOW and is provided with a small internal pull-up resistor. KEN# must satisfy setup and hold times t14 and t15 for proper operation. Cache Flush input forces the Embedded Write-Back Enhanced IntelDX4 processorto flush its entire internal cache. FLUSH# is active LOW and need only be asserted for one clock. FLUSH# is asynchronous but setup and hold times t20 and t21 must be met for recognition in any specific clock. Page Write-Through and Page Cache Disable pins reflect the state of the page attribute bits, PWT and PCD, in the page table entry, page directory entry or control register 3 (CR3) when paging is enabled. When paging is disabled, the Embedded Write-Back Enhanced IntelDX4 processorignores the PCD and PWT bits and assumes they are zero for the purpose of caching and driving PCD and PWT pins. PWT and PCD have the same timing as the cycle definition pins (M/IO#, D/C#, and W/R#). PWT and PCD are active HIGH and are not driven during bus hold. PCD is masked by the cache disable bit (CD) in Control Register 0. FLUSH# I PAGE CACHEABILITY PWT PCD O O .com 20 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 6 of 8) Symbol BS16# BS8# Type I I Name and Function Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the Embedded WriteBack Enhanced IntelDX4 processor to run multiple bus cycles to complete a request from devices that cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are sampled every clock. The processor uses the state of these pins in the clock before Ready to determine bus size. These signals are active LOW and are provided with internal pull-up resistors. These inputs must satisfy setup and hold times t14 and t15 for proper operation. Address Bit 20 Mask pin, when asserted, causes the Embedded Write-Back Enhanced IntelDX4 processorto mask physical address bit 20 (A20) before performing a lookup to the internal cache or driving a memory cycle on the bus. A20M# emulates the address wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is active LOW and should be asserted only when the Embedded Write-Back Enhanced IntelDX4 processoris in real mode. This pin is asynchronous but should meet setup and hold times t20 and t21 for recognition in any specific clock. For proper operation, A20M# should be sampled HIGH at the falling edge of RESET. BUS SIZE CONTROL ADDRESS MASK A20M# I t4U.com TEST ACCESS PORT TCK I D Test Clock, an input to the Embedded Write-Back Enhanced IntelDX4 processor, at provides the clocking function required by the JTAG Boundary scan feature. TCK is used to clock state information (via TMS) and data (via TDI) into the component .com on the rising edge of TCK. Data is clocked out of the component (via TDO) on the falling edge of TCK. TCK is provided with an internal pull-up resistor. Test Data Input is the serial input used to shift JTAG instructions and data into the processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR Test Access Port (TAP) controller states. During all other TAP controller states, TDI is a "don't care." TDI is provided with an internal pull-up resistor. Test Data Output is the serial output used to shift JTAG instructions and data out of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR TAP controller states. At all other times TDO is driven to the high impedance state. Test Mode Select is decoded by the JTAG TAP to select test logic operation. TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior of the TAP controller, TMS is provided with an internal pull-up resistor. The Floating Point Error pin is driven active when a floating point error occurs. FERR# is similar to the ERROR# pin on the Intel387TM Math CoProcessor. FERR# is included for compatibility with systems using DOS type floating point error reporting. FERR# will not go active if FP errors are masked in FPU register. FERR# is active LOW, and is not floated during bus hold. aShee TDI I TDO O TMS I NUMERIC ERROR REPORTING FERR# O .com .com DataSheet 4 U .com 21 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 7 of 8) Symbol IGNNE# Type I Name and Function When the Ignore Numeric Error pin is asserted the processor will ignore a numeric error and continue executing non-control floating point instructions, but FERR# will still be activated by the processor. When IGNNE# is de-asserted the processor will freeze on a non-control floating point instruction, if a previous floating point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 is set. IGNNE# is active LOW and is provided with a small internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t20 and t21 must be met to ensure recognition on any specific clock. The CACHE# output indicates internal cacheability on read cycles and burst writeback on write cycles. CACHE# is asserted for cacheable reads, cacheable code fetches and write-backs. It is driven inactive for non-cacheable reads, I/O cycles, special cycles, and write-through cycles. Cache FLUSH# is an existing pin that operates differently if the processor is configured as Enhanced Bus mode (write-back). FLUSH# causes the processor to write back all modified lines and flush (invalidate) the cache. FLUSH# is asynchronous, but must meet setup and hold times t20 and t21 for recognition in any specific clock. The Hit/Miss to a Modified Line pin is a cache coherency protocol pin that is driven only in Enhanced Bus mode. When a snoop cycle is run, HITM# indicates that the processor contains the snooped line and that the line has been modified. Assertion of HITM# implies that the line will be written back in its entirety, unless .com the processor is already in the process of doing a replacement write-back of the same line. The Invalidation Request pin is a cache coherency protocol pin that is used only in the Enhanced Bus mode. It is sampled by the processor on EADS#-driven snoop cycles. It is necessary to assert this pin to get the effect of the processor invalidate cycle on write-through-only lines. INV also invalidates the write-back lines. However, if the snooped line is modified, the line will be written back and then invalidated. INV must satisfy setup and hold times t12 and t13 for proper operation. In the Enhanced bus mode, Pseudo-Lock Output is always driven inactive. In this mode, a 64-bit data read (caused by an FP operand access or a segment descriptor read) is treated as a multiple cycle read request, which may be a burst or a non-burst access based on whether BRDY# or RDY# is returned by the system. Because only write-back cycles (caused by snoop write-back or replacement write-back) are write burstable, a 64-bit write will be driven out as two non-burst bus cycles. BLAST# is asserted during both writes. For the Embedded Write-Back Enhanced IntelDX4 processor, Soft RESET operates similar to other the Intel486 processors. On SRESET, the internal SMRAM base register retains its previous value, does not flush, write-back or disable the internal cache. Because SRESET is treated as an interrupt, it is possible to have a bus cycle while SRESET is asserted. SRESET is serviced only on an instruction boundary. SRESET is asynchronous but must meet setup and hold times t20 and t21 for recognition in any specific clock. WRITE-BACK ENHANCED MODE CACHE# O FLUSH# I t4U.com HITM# O DataShee INV I PLOCK# O SRESET I .com 22 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 8. Embedded Write-Back Enhanced IntelDX4TM Processor Pin Descriptions (Sheet 8 of 8) Symbol WB/WT# Type I Name and Function The Write-Back/Write-Through pin enables Enhanced Bus mode (write-back cache). It also defines a cached line as write-through or write-back. For cache configuration, WB/WT# must be valid during RESET and be active for at least two clocks before and two clocks after RESET is de-asserted. To define write-back or write-through configuration of a line, WB/WT# is sampled in the same clock as the first RDY# or BRDY# is returned during a line fill (allocation) cycle. The Clock Multiplier input, defined during device RESET, defines the ratio of internal core frequency to external bus frequency. If sampled low, the core frequency operates at twice the external bus frequency (speed doubled mode). If driven high, speed triple mode is selected. CLKMUL has an internal pull-up speed to VCC. A 10-K pullup resistor is recommended when the pin is tied high. The 5V reference voltage input is the reference voltage for the 5V-tolerant I/O buffers. This signal should be connected to +5V 5% for use with 5V logic. If all inputs are from 3V logic, this pin should be connected to 3.3V. A Voltage Detect signal allows external system logic to distinguish between a 5V Intel486 processor and the 3.3V IntelDX4 processor. This signal is active LOW for a 3.3V IntelDX4 processor. This pin is available only on the PGA version of the Embedded Write-Back Enhanced IntelDX4 processor. Reserved is reserved for future use. This pin MUST be connected to an external .com pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up resistor must be connected only to the RESERVED# pin. Do not share this resistor with other pins requiring pull-ups. CLKMUL, VCC5, AND VOLDET CLKMUL I VCC5 I VOLDET O t4U.com RESERVED PINS RESERVED# I DataShee .com .com DataSheet 4 U .com 23 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 9. Output Pins Output Signal Name BREQ HLDA BE3#-BE0# PWT, PCD W/R#, M/IO#, D/C# LOCK# PLOCK# ADS# BLAST# PCHK# FERR# A3-A2 Active Level HIGH HIGH LOW HIGH HIGH/LOW LOW LOW LOW LOW LOW LOW HIGH LOW LOW LOW LOW Floated During Address Hold Floated During Bus Hold During Stop Grant and Stop Clock States Previous State1 As per HOLD * * * * * * * Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State * * Previous State Previous State HIGH2 HIGH2 LOW t4U.com SMIACT# CACHE# HITM# VOLDET DataShee * * * .com * NOTES: 1. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating. 2. For the case of snoop cycles (via EADS#) during Stop Grant state, CACHE# and HITM# can go active depending on the snoop hit in the internal cache. Table 10. Input/Output Pins Output Signal Name D31-D0 DP3-DP0 A31-A4 Active Level HIGH HIGH HIGH * Floated During Address Hold Floated During Bus Hold * * * During Stop Grant and Stop Clock States Floated Floated Previous State NOTE: The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating. .com 24 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 11. Test Pins Name TCK TDI TDO TMS Input or Output Input Input Output Input Sampled/ Driven On N/A Rising Edge of TCK Failing Edge of TCK Rising Edge of TCK Table 12. Input Pins (Sheet 1 of 2) Name CLK RESET SRESET HOLD HIGH HIGH HIGH HIGH LOW Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Pull-Up Pull-Up Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Active Level Synchronous/ Asynchronous Internal Pull-Up/ Pull-Down t4U.com AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR NMI IGNNE# RESERVED# SMI# STPCLK# INV DataShee .com LOW LOW LOW LOW LOW LOW HIGH HIGH LOW LOW LOW LOW HIGH LOW NOTE: 1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-K pullup resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external 10-K pull-up resistor is recommended. .com .com DataSheet 4 U .com 25 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 12. Input Pins (Sheet 2 of 2) Name WB/WT# CLKMUL TCK TDI TMS Active Level HIGH/LOW HIGH HIGH HIGH HIGH Synchronous/ Asynchronous Synchronous Internal Pull-Up/ Pull-Down Pull-Down Pull-Up1 Pull-Up Pull-Up Pull-Up NOTE: 1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-K pullup resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external 10-K pull-up resistor is recommended. processor's ID Flag, which is bit 21 of the EFLAGS register. If software can change the value of this flag, the CPUID instruction is available. The actual state of the ID Flag bit is irrelevant and provides no signifiThe Embedded Write-Back Enhanced IntelDX4 cance to the hardware. This bit is cleared (reset to t4U.com processor architecture is essentially the same as the zero) upon device reset (RESET or SRESET) for IntelDX4 processor. Refer to the Embedded compatibility with Intel486 processor designs that do Intel486TM Processor Family Developer's Manual .comthe CPUID instruction. not support (273021) 4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW DataShee The Embedded Write-Back Enhanced IntelDX4 processor has one pin reserved for possible future use. This pin, an input signal, is called RESERVED# and must be connected to a 10-K pull-up resistor. The pull-up resistor must be connected only to the RESERVED# pin. Do not share this resistor with other pins requiring pull-ups. CPUID-instruction details are provided here for the Embedded Write-Back Enhanced IntelDX4 processor. Refer to Intel Application Note AP-485 Intel Processor Identification with the CPUID Instruction (Order No. 241618) for a description that covers all aspects of the CPUID instruction and how it pertains to other Intel processors. 4.1.1 Operation of the CPUID Instruction 4.1 CPUID Instruction The Embedded Write-Back Enhanced IntelDX4 processor supports the CPUID instruction (see Table 13). Because not all Intel processors support the CPUID instruction, a simple test can determine if the instruction is supported. The test involves the The CPUID instruction requires the software developer to pass an input parameter to the processor in the EAX register. The processor response is returned in registers EAX, EBX, EDX, and ECX. Table 13. CPUID Instruction Description OP CODE 0F A2 Instruction CPUID Processor Core Clocks 9 14 9 Parameter passed in EAX (Input Value) Description Vendor (Intel) ID String Processor Identification Undefined (Do Not Use) 0 1 >1 .com 26 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Vendor ID String - When the parameter passed in EAX is 0 (zero), the register values returned upon instruction execution are shown in the following table. 31-------------24 High Value (= 1) Vendor ID String (ASCII Characters) EAX EBX EDX ECX 0000 u (75) I (49) l (6C) 23-----------16 0000 n (6E) e (65) e (65) 15--------------8 0000 e (65) n (6E) t (74) 7--------------0 0001 G (47) i (69) n (6E) The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to the string "GenuineIntel." The state of the WB/WT# input pin is sampled by the processor on the falling edge of the RESET signal. If WB/WT# is LOW, the processor is configured to operate in Write-Through/Standard Bus mode. If HIGH, it is configured to operate in Write-Back/Enhanced Bus mode. The value of the "Model" field of the processor signature register depends on the bus mode for which the processor is configured. Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon instruction execution are: t4U.com Processor Signature for Write-Through/Standard Bus mode Processor Signature for WriteBack/Enhanced Bus mode EAX 31---------------------------14 (Do Not Use) Intel Reserved 13,12 00 Processor 11----8 0100 Family 7----4 1000 Model 3----0 XXXX Stepping DataShee .comType 00 (Do Not Use) Intel Reserved 0100 Family 1001 Model XXXX Stepping Processor Type (Intel releases information about stepping numbers as needed) 31--------------------------------------------------------------------------------------------------0 Intel Reserved (Do Not Use) EBX ECX Intel Reserved Intel Reserved 31----------------------------------------------------------------------------2 Feature Flags EDX 0------------------------------------------------------------------------------0 1 1 VME 0 0 FPU .com .com DataSheet 4 U .com 27 www..com Embedded Write-Back Enhanced IntelDX4TM Processor 4.2 Identification After Reset 31---------------------------14 13,12 00 Processor Type 11----8 0100 Family 7----4 1000 Model 3----0 XXXX Stepping Processor Identification - Upon reset, the EDX register contains the processor signature: Processor Signature for Write-Through/Standard Bus mode Processor Signature for WriteBack/Enhanced Bus mode EDX (Do Not Use) Intel Reserved (Do Not Use) Intel Reserved 00 Processor Type 0100 Family 1001 Model XXXX Stepping (Intel releases information about stepping numbers as needed) 4.3 4.3.1 Boundary Scan (JTAG) Device Identification t4U.com Tables 14 and 15 show the 32-bit code for the Embedded Write-Back Enhanced IntelDX4 processor. This code is loaded into the Device Identification Register. DataShee .com Table 14. Boundary Scan Component Identification Code (Write-Through/Standard Bus Mode) Version VCC 1=3.3 V Part Number Mfg ID Model 01000 = Embedded WriteBack Enhanced IntelDX4 processor 16--------12 01000 009H = Intel 1 Intel Architecture Type 26-----------21 000001 Family 0100 = Intel486 CPU Family 31----28 XXXX 27 1 20----17 0100 11------------1 00000001001 0 1 (Intel releases information about version numbers as needed) Boundary Scan Component Identification Code = x828 8013 (Hex) .com 28 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 15. Boundary Scan Component Identification Code (Write-Back/Enhanced Bus Mode) Version VCC 1=3.3 V Intel Architecture Type Part Number Family 0100 = Intel486 CPU Family Model 01001 = Embedded WriteBack Enhanced IntelDX4 processor 16--------12 01001 Mfg ID 009H = Intel 1 31----28 XXXX 27 1 26-----------21 000001 20----17 0100 11------------1 00000001001 0 1 (Intel releases information about version numbers as needed) Boundary Scan Component Identification Code = x828 9013 (Hex) 4.3.2 Boundary Scan Register Bits and Bit Order t4U.com TDO The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are "Reserved" bits which correspond to no-connect (N/C) signals of the Embedded Write-Back Enhanced IntelDX4 processor. Control registers WRCTL, ABUSCTL, BUSCTL, and MISCCTL are used to select the .com direction of bidirectional or three-state output signal pins. A "1" in these cells designates that the associated bus or bits are floated if the pins are three-state, or selected as input if they are bidirectional. * WRCTL controls D31-D0 and DP3-DP0 * ABUSCTL controls A31-A2 * BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W/R#, BE0#, BE1#, BE2#, BE3#, M/IO#, D/C#, PWT, PCD, and CACHE# * MISCCTL controls PCHK#, HLDA, BREQ, and HITM# The following is the bit order of the Embedded WriteBack Enhanced IntelDX4 processor boundary scan register: A2, A3, A4, A5, RESERVED#, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DataShee DP0, D0, D1, D2, D3, D4, D5, D6, D7, DP1, D8, D9, D10, D11, D12, D13, D14, D15, DP2, D16, D17, D18, D19, D20, D21, D22, D23, DP3, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, IGNNE#, INV, CACHE#, FERR#, SMI#, WB/WT#, HITM#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D/C#, M/IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W/R#, HLDA, CLK, AHOLD, HOLD, KEN#, RDY#, CLKMUL, BS8#, BS16#, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL TDI .com .com DataSheet 4 U .com 29 www..com Embedded Write-Back Enhanced IntelDX4TM Processor 5.0 5.1 ELECTRICAL SPECIFICATIONS Maximum Ratings 5.2 DC Specifications Table 16 is a stress rating only. Extended exposure to the Maximum Ratings may affect device reliability. Furthermore, although the Embedded Write-Back Enhanced IntelDX4 processorcontains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. Functional operating conditions are given in Section 5.2, DC Specifications and Section 5.3, AC Specifications. Table 16. Absolute Maximum Ratings Case Temperature under Bias Storage Temperature t4U.com DC Voltage on Any Pin with Respect to Ground Supply Voltage VCC with Respect to VSS Reference Voltage VCC5 with Respect to VSS Transient Voltage on any Input -65 C to +110 C -65 C to +150 C -0.5 V to VCC5 + 0.5 V -0.5 V to +4.6 V -0.5 V to +6.5 V The lesser of: VCC5 + 1.6 V or 6.5 V 55 mA The following tables show the operating supply voltages, DC I/O specifications, and component power consumption for the Embedded Write-Back Enhanced IntelDX4 processor. Table 17. Operating Supply Voltages Product x80486DX4WB75 x80486DX4WB100 x0486DX4WB100 3.3 V 3.3 V 3.3 V VCC 0.3 V 0.3 V 0.3 V NOTE: To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". DataShee .com Current Sink on VCC5 .com 30 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 18. DC Specifications Functional Operating Range: VCC = 3.3 V 0.3 V; VCC5 = 5 V 0.25 V (Note 1); TCASE=0 C to +85 C Symbol VIL VIH VIHC VOL Parameter Input LOW Voltage Input HIGH Voltage Input HIGH Voltage of CLK Output LOW Voltage IOL = 4.0 mA (Address, Data, BEn) IOL = 5.0 mA (Definition, Control) IOL = 2.0 mA IOL = 100 A Min. -0.3 2.0 VCC5 -0.6 Typ. Max. +0.8 VCC5 +0.3 VCC5 +0.3 0.45 0.45 0.40 0.20 Unit V V V Notes Note 2 V V V V VOH ICC5 ILI Output HIGH Voltage IOH = -2.0 mA VCC5 Leakage Current Input Leakage Current Input Leakage Current SRESET 2.4 15 300 15 200 300 400 V A A A A A A pF pF pF Note 7 Note 7 Note 7 Note 3 Note 4 Note 5 Note 5 Note 6 t4U.com IIH IIL ILO CIN COUT CCLK DataShee Input Leakage Current Output Leakage Current Input Capacitance I/O or Output Capacitance CLK Capacitance .com 15 10 14 12 NOTES: 1. VCC5 should be connected to 3.3 V 0.3 V in 3.3 V-only systems. 2. All inputs except CLK. 3. This parameter is for inputs without pull-up or pull-down resistors and 0V VIN VCC. 4. This parameter is for VCC5 - VCC 2.25 V. Typical value is not 100% tested. 5. This parameter is for inputs with pull-down resistors and VIH = 2.4V. 6. This parameter is for inputs with pull-up resistors and VIL = 0.4V. 7. FC=1 MHz. Not 100% tested. .com .com DataSheet 4 U .com 31 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 19. ICC Values Functional Operating Range: VCC = 3.3 V 0.3 V; VCC5 = 5 V 0.25 V (Note 1); TCASE = 0C to +85C Parameter ICC Active (Power Supply) ICC Active (Thermal Design) ICC Stop Grant ICC Stop Clock Operating Frequency 75 MHz 100 MHz 75 MHz 100 MHz 75 MHz 100 MHz 0 MHz 825 mA 1075 mA 20 mA 50 mA 600 A Typ. Maximum 1100 mA 1450 mA 975 mA 1300 mA 75 mA 100 mA 2 mA Notes Note 2 Notes 3, 4, 5 Note 6 Note 7 NOTES: 1. VCC5 should be connected to 3.3 V 0.3 V in 3.3 V-only systems. 2. This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 3.6V. 3. The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix at VCC = 3.3V. 4. The typical current column is the typical operating current in a system. This value is measured in a system using a typical device at VCC = 3.3V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific system configuration. 5. U.com Typical values are not 100% tested. t4 6. The ICC Stop Grant specification refers to the ICC value once the Embedded Write-Back Enhanced IntelDX4 processor enters the Stop Grant or Auto HALT Power Down state. 7. The ICC Stop Clock specification refers to the ICC value once the Embedded Write-Back Enhanced IntelDX4 processor .com enters the Stop Clock state. The VIH and VIL levels must be equal to VCC and 0 V, respectively, in order to meet the ICC Stop Clock specifications. DataShee .com 32 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor 5.3 AC Specifications The AC specifications for the Embedded Write-Back Enhanced IntelDX4 processor are given in this section. Table 20. AC Characteristics VCC = 3.3 V 0.3 V; VCC5 = 5 V 0.25 V (Note 1) TCASE = 0C to +85C; CL = 50pF, unless otherwise specified. (Sheet 1 of 2) Product Symbol Parameter CLK Frequency t1 t1a CLK Period CLK Period Stability WB75 Min 8 40 Max 25 125 250 WB100 Min 8 30 Max 33 125 250 Unit MHz ns ps 4 4 Adjacent clocks Note 3 t2 t3 CLK High Time CLK Low Time CLK Fall Time CLK Rise Time 14 14 4 4 3 11 11 3 3 14 ns ns ns ns ns 4 4 4 4 8 at 2V at 0.8V 2V to 0.8V Figure Notes Note 2 t4U.com t4 t5 t6 DataShee 0.8V to 2V .com 3 19 A31-A2, PWT, PCD, BE3-BE0#, M/IO#, D/C#, W/R#, ADS#, LOCK#, FERR#, CACHE#, HITM#, BREQ, HLDA Valid Delay A31-A2, PWT, PCD, BE3-BE0#, M/IO#, D/C#, W/R#, ADS#, LOCK#, CACHE# Float Delay PCHK# Valid Delay BLAST#, PLOCK#, SMIACT# Valid Delay BLAST#, PLOCK# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS#, INV Setup Time EADS#, INV Hold Time KEN#, BS16#, BS8#, WB/WT# Setup Time KEN#, BS16#, BS8#, WB/WT# Hold Time RDY#, BRDY# Setup Time RDY#, BRDY# Hold Time 8 3 8 3 8 3 3 3 3 28 t7 20 ns 9 Note 3 t8 t8a t9 t10 t11 t12 t13 t14 t15 t16 .com t17 24 24 28 20 28 3 3 14 14 20 ns ns ns ns ns ns ns ns ns ns ns 7 8 9 8 9 5 5 5 5 6 6 33 Note 3 Note 3 3 14 20 5 3 5 3 5 3 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 20. AC Characteristics VCC = 3.3 V 0.3 V; VCC5 = 5 V 0.25 V (Note 1) TCASE = 0C to +85C; CL = 50pF, unless otherwise specified. (Sheet 2 of 2) Product Symbol t18 t18a t19 t20 Parameter HOLD, AHOLD Setup Time BOFF# Setup Time HOLD, AHOLD, BOFF# Hold Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET, IGNNE# Setup Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET, IGNNE# Hold Time D31-D0, DP3-DP0, A31-A4 Read Setup Time D31-D0, DP3-DP0, A31-A4 Read Hold Time 8 8 3 8 WB75 Min Max WB100 Min 6 7 3 5 Max Unit ns ns ns ns Figure 5 5 5 5 Note 4 Notes t21 3 3 ns 5 Note 4 t22 t23 5 3 5 3 ns ns 6 5 6 5 t4U.com DataShee NOTES: 1. VCC5 should be connected to 3.3 V 0.3 V in 3.3 V-only systems. .com 2. 0-MHz operation is guaranteed when the STPCLK# and Stop Grant bus cycle protocol is used. 3. Not 100% tested, guaranteed by design characterization. 4. A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET). Power-up resets (cold resets) require RESET to be asserted for at least 1 ms after VCC and CLK are stable. .com 34 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 21. AC Specifications for the Test Access Port VCC = 3.3 V 0.3 V; VCC5 = 5 V 0.25 V (Note 1) TCASE = 0C to +85C; CL = 50 pF Symbol t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 TCK Frequency TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Outputs (except TDO) Valid Delay All Outputs (except TDO) Float Delay All Inputs (except TDI, TMS, TCK) Setup Time All Inputs (except TDI, TMS, TCK) Hold Time 8 7 3 8 7 3 25 30 25 36 40 10 10 4 4 Parameter Min Max 25 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 10 11 11 11 11 11 11 11 11 @ 2.0V @ 0.8V Note 3 Note 3 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Note 4 Figure Notes Note 2 t4U.com DataShee NOTES: 1. VCC5 should be connected to 3.3 V 0.3 V in 3.3 V-only systems. All inputs and outputs are TTL level. 2. TCK period CLK period. .com 3. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase in TCK period. 4. Parameters t 30 - t37 are measured from TCK. .com .com DataSheet 4 U .com 35 www..com Embedded Write-Back Enhanced IntelDX4TM Processor CLK 2.0 V 1.5 V 0.8 V t2 t5 t1 tx ty t4 t3 2.0 V 1.5 V 0.8 V 1.5 V tx = input setup times ty = input hold times, output float, valid and hold times Figure 4. CLK Waveform t4U.com Tx CLK x x .com DataShee T T Tx t12 INV, EADS# t13 t14 BS8#, BS16#, KEN#, WB/WT# t15 t18 BOFF#, AHOLD, HOLD t19 RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET, IGNNE# A31-A4 (READ) t20 t21 t22 t23 Figure 5. Input Setup and Hold Timing .com 36 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor T2 CLK Tx Tx t16 RDY#, BRDY# t17 1.5 V t22 D31-D0, DP3-DP0 t23 1.5 V Figure 6. Input Setup and Hold Timing T2 Tx Tx Tx t4U.com CLK DataShee .com RDY#, BRDY# D31-D0 DP3-DP0 t8 VALID MIN MAX PCHK# VALID Figure 7. PCHK# Valid Delay Timing .com .com DataSheet 4 U .com 37 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Tx CLK Tx Tx Tx MIN A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, BREQ, HLDA, FERR#, CACHE#, HITM# t6 MAX VALID n VALID n+1 MIN t10 MAX D31-D0, DP3-DP0 VALID n VALID n+1 MIN t8a MAX t4U.com SMIACT#, BLAST#, PLOCK# VALID n VALID n+1 DataShee .com Figure 8. Output Valid Delay Timing Tx CLK MIN Tx Tx A2-A31, PWT, PCD, BE0-3#, M/IO#, D/C#, W/R#, ADS#, LOCK#, CACHE# t6 t7 VALID t10 MIN t11 D31-D0, DP3-DP0 VALID MIN t8a t9 BLAST#, PLOCK# VALID Figure 9. Maximum Float Delay Timing .com 38 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor 2.0 V 2.0 V t27 TCK 0.8 V t28 t26 t29 0.8 V t25 Figure 10. TCK Waveform TCK 1.5 V t4U.com t 30 TMS TDI t32 t31 VALID DataShee t 33 .com TDO t34 OUTPUT t36 INPUT VALID VALID t37 VALID t35 VALID Figure 11. Test Signal Timing Diagram .com .com DataSheet 4 U .com 39 www..com Embedded Write-Back Enhanced IntelDX4TM Processor 5.4 Capacitive Derating Curves These graphs are the capacitive derating curves for the Embedded Write-Back Enhanced IntelDX4 processor. nom+7 nom+6 nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 Capacitive Load (pF) 125 150 t4U.com Note: This graph will not be linear outside of the capacitive range shown. nom = nominal value from the AC Characteristics table. DataShee A3238-01 .com Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition nom+5 nom+4 Delay (ns) nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 125 150 Capacitive Load (pF) Note: This graph will not be linear outside of the capacitive range shown. nom = nominal value from the AC Characteristics table. A3237-01 Figure .com 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition 40 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor In a mixed voltage system (processors at 3 volts, peripherals at 5 volts), the bus is driven to 5 volts by the peripheral logic. Therefore, the processor must discharge the capacitance on the bus from 5 volts to 0 volts, which takes more time than the 3 volts to 0 volts transition. Inaccurate capacitive derating impacts timing margins and may result in system failures under certain load conditions. When designing for higher loads in mixed voltage systems, timing margins should be evaluated based on the derating curves shown in Figure 14. For more accurate delay prediction, use I/O buffer models. t4U.com DataShee .com Figure 14. Typical Loading Delay versus Load Capacitance in Mixed Voltage System .com .com DataSheet 4 U .com 41 www..com Embedded Write-Back Enhanced IntelDX4TM Processor 6.0 MECHANICAL DATA This section describes the packaging dimensions and thermal specifications for the Embedded Write-Back Enhanced IntelDX4 processor. 6.1 Package Dimensions 30.6 0.25 28.0 0.10 1.14 (ref) 1 25.50 (ref) 208 21.20 0.10 157 .40 Min 0.13 + 0.12-0.08 156 0 Min 7 Max t4U.com Top View 0.60 0.10 1.30 Ref 0.50 DataShee .com Metal Heat Spreader 3.37 0.08 3.70 Max 52 105 0.13 Min 0.25 Max 53 104 NOTE: Length measurements same as width measurements 1.76 Max Tolerance Window for Lead Skew from Theoretical True Position 0.10 Max Units: mm A3260-01 Figure 15. 208-Lead SQFP Package Dimensions .com 42 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor t4U.com DataShee .com Figure 16. Principal Dimensions and Data for 168-Pin Grid Array Package Table 22. 168-Pin Ceramic PGA Package Dimensions Symbol A A1 A2 A3 B D D1 e1 L N S1 1.52 Millimeters Min 3.56 0.64 2.8 1.14 0.43 44.07 40.51 2.29 2.54 168 2.54 0.060 Max 4.57 1.14 3.5 1.40 0.51 44.83 40.77 2.79 3.30 SOLID LID SOLID LID Notes Min 0.140 0.025 0.110 0.045 0.017 1.735 1.595 0.090 0.100 168 0.100 Inches Max 0.180 0.045 0.140 0.055 0.020 1.765 1.605 0.110 0.130 SOLID LID SOLID LID Notes .com .com DataSheet 4 U .com 43 www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 23. Ceramic PGA Package Dimension Symbols Letter or Symbol A A1 A2 A3 B D D1 e1 L S1 Description of Dimensions Distance from seating plane to highest point of body Distance between seating plane and base plane (lid) Distance from base plane to highest point of body Distance from seating plane to bottom of body Diameter of terminal lead pin Largest overall package dimension of length A body length dimension, outer lead center to outer lead center Linear spacing between true lead position centerlines Distance from seating plane to end of lead Other body dimension, outer lead center to edge of body t4U.com NOTES: 1. Controlling dimension: millimeter. 2. Dimension "e1" ("e") is non-cumulative. 3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415-0.0430 inch. 4. Dimensions "B", "B1" and "C" are nominal. 5. Details of Pin 1 identifier are optional. DataShee .com 6.2 Package Thermal Specifications Values for JA and JC are given in the following tables for each product at its maximum operating frequencies. Maximum TA is shown for each product operating at its maximum processor frequency (three times the CLK frequency). Refer to the Embedded Intel486TM Processor Family Developer's Manual (273021) for a description of the methods used to measure these characteristics. The Embedded Write-Back Enhanced IntelDX4 processoris specified for operation when the case temperature (TC ) is within the range of 0C to 85C. TC may be measured in any environment to determine whether the processor is within the specified operating range. The ambient temperature (TA) can be calculated from JC and JA from the following equations: TJ = TC + P * JC TA = TJ - P * JA TC = TA + P * [JA - JC] TA = TC - P * [JA - JC] Where TJ , TA, TC equals Junction, Ambient and Case Temperature respectively. JC, JA equals Junction-to-Case and Junction-to-Ambient thermal Resistance, respectively. P is defined as Maximum Power Consumption. .com 44 .com DataSheet 4 U .com www..com Embedded Write-Back Enhanced IntelDX4TM Processor Table 24. Thermal Resistance, JA (C/W) JA vs. Airflow -- ft/min. (m/sec) Package 168-Pin PGA 168-Pin PGA 208-Lead SQFP 208-Lead SQFP Heat Sink No Yes No Yes 0 (0) 17.5 13.5 12.5 10.5 200 (1.01) 15.0 8.5 10.0 6.5 400 (2.03) 13.0 6.5 9.0 5.0 600 (3.04) 11.5 5.5 8.5 4.0 800 (4.06) 10.0 4.5 1000 (5.07) 9.5 4.25 Table 25. Thermal Resistance, JC (C/W) Package 168-Pin PGA 168-Pin PGA 208-Lead SQFP Heat Sink No Yes No Yes JC 2.0 2.0 1.2 0.8 t4U.com 208-Lead SQFP .com Table 26. Maximum Tambient, TA max (C) Airflow -- ft/min. (m/sec) Package 168-Pin PGA 168-Pin PGA 208-Lead SQFP 208-Lead SQFP 208-Lead SQFP 208-Lead SQFP Heat Sink No Yes No Yes No Yes Freq. (MHz) 100 100 100 100 75 75 0 (0) 18.5 35.5 36.5 43.5 200 (1.01) 29.0 57.0 46.0 60.5 400 (2.03) 37.5 65.5 50.0 67.0 600 (3.04) 44.0 70.0 52.5 71.0 .com .com DataSheet 4 U .com 45 |
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